Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Business Wire

Faraday Unveils Design Implementation Services for FinFET Technology Targeting All Foundries

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, announced its debut of its design implementation services for FinFET ...
EDN

Partitioning an ASIC Design into Multiple FPGAs

Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before ...
EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Semiconductor Engineering

SpyGlass Application In An FPGA To ASIC Conversion Flow

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping ...
Electronic Design

Changing Requirements for ASIC Design

It’s a changing world. In 1851, the headline of an editorial in an Indiana newspaper urged readers to “Go West, Young Man!” Fast forward 150 years, and you ...
Ars Technica

ASIC design/verification or embedded systems programming

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
TheLadders.com

Senior ASIC Design Engineer

About Recogni:Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different ...