In this column, we take a closer look as to how timing and delays affect our logic circuits. As part of this, we start to consider the timing diagrams presented in data sheets. As I was writing my ...

There are many parameters, both electrical and physical, that contribute to the relative size of tDV and not all scale with operating speed. Factors such as signal noise, crosstalk, skew, jitter, and ...

Who would have thought that a circuit comprising only two 2-input NAND gates could be so complicated (or, should we say, “interesting”)? Up to this point (click here to see my earlier columns), the ...