Electronic Design

What’s The Difference Between ATPG And Logic BIST?

Two test strategies are used to test virtually all IC logic: automatic test pattern generation (ATPG) with test pattern compression and logic built-in self-test (BIST). This article will describe how ...
Semiconductor Engineering

Improve Logic Test With A Hybrid ATPG/BIST Solution

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a ...
Electronic Design

Combining Logic BIST and Scan Test Compression

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...
EDN

New test points slash ATPG test pattern count

Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...
Semiconductor Engineering

Scalable End-To-End Test Solutions For Today’s Complex SoCs

Left-shifting DFT, scalable tests from manufacturing to the field, enabling system-level tests for in-field debug.
EDN

Design for test boot camp, part 1: Scan test

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often write about various aspects of digital IC test. If you started following the Test Voices blog when it was part of Test & ...