Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Business Wire

Cypress' HyperBus™ Memory Interface for Instant-on Applications Incorporated into JEDEC xSPI Electrical Interface Standard

SAN JOSE, Calif.--(BUSINESS WIRE)--Cypress Semiconductor Corp. (Nasdaq: CY), a global leader in embedded systems solutions, today announced the inclusion of Cypress' high-bandwidth HyperBus™ 8-bit ...
Business Wire

Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs

SAN JOSE, Calif.--(BUSINESS WIRE)--Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the expansion of its DDR5 memory interface chip ...
Electronic Design

Leverage High-Frequency Source-Synchronous Memory in SoC Design

Download this article in PDF format. Today’s embedded systems require high external memory bandwidth to achieve fast boot time and application loading time with minimal cost. Historically, ...