EDN

ASIC vendors heed call for virtual prototyping tools

SAN MATEO, Calif. — If time is money and product development budgets are being slashed, it follows that the time it takes to design and tape out a custom chip should fall too. That's no easy task as ...
TMCnet

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes remain committed to advancing verification methodologies and providing scalable, efficient, and robust development tools for the RISC-V community. Together, the companies ...
EDN

The virtues of silicon virtual prototyping

Fig. 1. Silicon virtual prototyping gives advanced insight into the place and rout process to reduce the number and length of design iterations. Silicon virtual prototyping is the process of providing ...
Electronic Design

FPGAs And Virtual Prototypes Share Common Design Space

Much has been written about the rise of field-programmable-gate-array (FPGA) -based platforms over application-specific-integrated-circuit (ASIC) implementations. During the last few years, FPGAs have ...
Business Wire

Aldec Cuts ASIC Design Prototype Bring-Up Time with HES-DVM’s Automatic Partitioning Tool and Faster HDL-to-FPGA Compilation Times

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...
Electronic Design

Virtual Prototypes Cut Software Bottleneck

High-speed, pre-silicon system models help developers start software development earlier and ensure timely product release. As the software content in today's 2.5G and 3G phones rapidly increases, ...