EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
EDN

Partitioning an ASIC Design into Multiple FPGAs

Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before ...
Design-Reuse

Magma's Blast Create SA Used by STMicroelectronics to Deliver Industry's First Application-Specific Structured ASIC

Integrated flow proven to deliver better timing, area and turnaround time for structured ASIC designs SANTA CLARA, Calif., July 21, 2006 ––Magma® Design Automation Inc. (Nasdaq: LAVA), a provider ...
Business Wire

Faraday Unveils Design Implementation Services for FinFET Technology Targeting All Foundries

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, announced its debut of its design implementation services for FinFET ...
Design-Reuse

Faraday Announces Successful Implementation of 533 MHz ARM(R) Compliant Core -- FA626 in 130nm SoC ASIC

HSINCHU, Taiwan and SUNNYVALE -- May 13, 2008 -- Faraday Technology (TAIEX: 3035), a leading ASIC and IP provider, today announced that it has successfully integrated a hardened 533Mhz ARM(R) ...
Semiconductor Engineering

SpyGlass Application In An FPGA To ASIC Conversion Flow

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping ...
Ars Technica

ASIC design/verification or embedded systems programming

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...