IEEE

Ultra-Scale ($0.014 \mu ~\mathrm{m}^{2}$) High-Efficient 10A 6T Cfet-Sram Cells Combined Backside Power Deliver Networks and Backside Bit-Lines

Abstract: We design ultra-scale high-efficient 10A 6T CFETSRAM with both backside power deliver networks and backside bit-lines. About Frontside Power Delivery Network (FS-PDN) and Buried Power Rail ...
IEEE

D2D Variation Aware DTCO for Novel Vertical a-IGZO-FETs in Large-Scale M3D 2TOC DRAM Bit Cell Evaluation via Statistical Modeling Methodology

Abstract: Device nonuniformity of ultra-scaled novel vertical a-IGZO-FETs is induced by multi-sources, such as dimension variation and material disorder, limiting large-scale DRAM design. Particularly ...