IEEE

Design and simulation of digital frequency meter using VHDL

Abstract: The main aim of this paper is to design the digital frequency meter with frequency analyzing module. As a measuring frequency's instrument, the cymometer often refer to as electronic counter ...
IEEE

FPGA memory testing technique using BIST

Abstract: The wide use of Field Programmable Gate Arrays (FPGAs) in critical applications including, military and airborne applications require fault free operation of the FPGA. In FPGAs, faults can ...
GitHub

A VHDL parser for syntax highlighting.

Neovim, using nvim-treesitter and a Tokyo Night colour scheme: Neovim, using nvim-treesitter and a One Dark colour scheme: If you'd like your favourite colour scheme to be listed here, issue a PR with ...
GitHub

ghdl-yosys-plugin: VHDL synthesis (based on

This is experimental and work in progress! See ghdl.github.io/ghdl: Using/Synthesis. TODO: Create table with features of VHDL that are supported, WIP and pending. NOTE: GHDL must be built with at ...